SureCore and Sarcina Join Forces to Revolutionize Cryogenic Chip Packaging for Quantum Computing
2024-12-17
Author: Mei
In a groundbreaking partnership, SureCore, a leader in low-power semiconductor design, has teamed up with Sarcina Technology, renowned for their expertise in advanced packaging, to create custom packaging solutions for cryogenic chips. This collaboration is set to significantly impact the Quantum Computing (QC) landscape.
On December 17, 2024, SureCore announced the success of its Cryogenic IP evaluation using test chips manufactured in both 180 nm and 22 nm process nodes. Paul Wells, CEO of SureCore, emphasized that this partnership is crucial for making Cryo-CMOS technology accessible within the Quantum Computing ecosystem. “Our CryoMem™ memory IP is not only silicon-proven but also reflects our expertise in library recharacterization services,” Wells stated. This technology enables the design of control and interface chips essential for manipulating qubits in extreme low-temperature environments.
Sarcina's CEO, Larry Zu, highlighted the company’s reputation for pushing the limits of packaging technology. "We've developed a specialized BGA package for cryogenic temperatures that sets a new standard in the industry," he explained. This coupling of SureCore's innovative memory design and Sarcina’s packaging prowess paves the way for developing cutting-edge chips capable of operating effectively within cryostats, ensuring efficiency and durability.
The initiative is part of an IUK-funded consortium aimed at creating a comprehensive ecosystem to foster the development of cryo-tolerant semiconductor intellectual property. This project seeks to deliver a suite of foundational IP that can be licensed, thereby enhancing competitive advantages for designers in the rapidly evolving Quantum Computing sector.
SureCore's advancements include developing embedded Static Random Access Memory (SRAM) that operates efficiently from 77K (-196°C) to near absolute zero, making it a critical component for digital subsystems in Quantum Computing. The recharacterization of standard and IO cell libraries for cryogenic environments facilitates a seamless RTL to GDSII design flow that is indispensable for the quantum sector's rapid growth.
One of the most significant challenges in scaling quantum technologies is the need for close proximity between control electronics and qubits, which must remain at cryogenic temperatures within a cryostat. To achieve this, the power consumption of control chips must be minimized to prevent excess thermal load, a challenge SureCore's low-power design illustrates its capacity to resolve effectively.
Historically, QC designs have necessitated room temperature electronics, resulting in costly and cumbersome cabling running between the control units and the qubits. However, with the advent of these custom cryogenic control SoCs housed within the cryostat, developers can anticipate substantial reductions in cost, size, and latency—three critical factors for performance improvement in quantum systems. The next critical phase will involve characterizing demonstration chips at cryogenic conditions to refine models for enhanced functionality.
As the industry continues to embrace quantum technologies, the collaboration between SureCore and Sarcina is poised to lead to unprecedented advancements in chip design and packaging, sequentially accelerating the growth of Quantum Computing capabilities.
Stay tuned for more updates on how this partnership is set to change the landscape of quantum technologies! Want to learn more about the implications of cryogenic technology in Quantum Computing? Visit SureCore’s website today!